`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/26 22:15:07
// Design Name: 
// Module Name: F_D
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "defines.vh"

module F_D(
    input   logic               clk,res,
    input   logic               en,
    input   logic               clr,

    input   logic [31: 0]       pc_f,
    input   logic [31: 0]       pc_read_f,
    input   logic [31: 0]       pc_plus4_f,
    input   logic [`EXCS_BUS]   excs_f,

    output  logic [31: 0]       pc_d,
    output  logic [31: 0]       instr_d,
    output  logic [31: 0]       pc_plus4_d,
    output  logic [`EXCS_BUS]   excs_d
    );

    always @(posedge clk,posedge res) begin
        if (res) begin
            pc_d        <= 32'b0;
            instr_d     <= 32'b0;
            pc_plus4_d  <= 32'b0;
            excs_d      <= 0;
        end 
        else if(clr) begin
            pc_d        <= 32'b0;
            instr_d     <= 32'b0;
            pc_plus4_d  <= 32'b0;
            excs_d      <= 0;
        end 
        else if (en) begin
            pc_d        <= pc_f;
            instr_d     <= pc_read_f;
            pc_plus4_d  <= pc_plus4_f;
            excs_d      <= excs_f;
        end      
    end

endmodule
